In stacked silicon interconnect technology, multiple integrated circuit (IC) dice are stacked, and the signals between the dice and signals input to and output from the packages are transmitted using multiple levels of interconnects. In an example package, an interposer is mounted on a package substrate, and one or more application ICs are mounted on the interposer. Such application ICs may be application specific integrated circuits (ASICs) or programmable ICs such as processors and programmable logic devices, for example.
The IC dice may be mounted on the interposer with copper pillars, the interposer may be mounted on the package substrate with C4 solder bumps, and the package substrate may have a ball grid array for connecting to a printed circuit board, for example. The interconnect between the IC dice and the interposer (e.g., the copper pillars) may be referred to as the level 0 interconnect, the interconnect between the interposer and the package substrate may be referred to as the level 1 interconnect, and the solder bumps for connecting the package substrate to an application substrate may be referred to as the level 2 interconnect. The three levels of interconnects present reliability challenges. Examples include failure of the level 0 interconnects due to metallurgical changes, delamination of the level 1 interconnects leading to bridging of the solder bumps, and stress induced cracks in the level 2 interconnects.
Reliability testing of an IC package having stacked dice can be challenging since different test apparatus are used to test the level 0, 1, and 2 interconnects. In one approach, the package is placed in a test chamber in which environmental parameters such as temperature and humidity can be controlled. After subjecting the package to the desired environmental conditions for the desired period of time, component level testing is performed on the package by removing the package from the test chamber and connecting the ball grid array of the package to probes of a test platform. The test platform transmits and receives signals via the probes, package substrate, and interposer to the IC dice of the package. This effectively tests the level 0 and level 1 interconnects. However, this approach does not replicate the level 2 interconnect as the ball grid array would be connected to a printed circuit board in a system end product.
In another approach, the interposer and IC dice are mounted on a daisy chain substrate instead of the package substrate that would be used in an end product, and the resulting package is mounted on a board level reliability (BLR) test board. After subjecting the package to the desired environmental conditions for the desired period of time, the package is removed from the test chamber, and probes of the test platform are connected to probe pads on the BLR test board. The test platform transmits and receives signals via the probes and daisy chain substrate. The BLR test board approach tests the reliability of the level 2 interconnects in a structure similar to the package being situated in an end product. However, the BLR testing does not test the reliability of the IC dice and interposer.